EPROMs are well known. One challenge in EPROMs is to obtain a very dense EPROM, thereby to reduce the die size for a given number of memory cells, or to increase the number of memory cells capable of being formed in a die of a given size. U.S. Pat. application Ser. No. 07/539,657 filed Jun. 13, 1990, discloses a particularly dense EPROM, wherein the select transistor normally 5 associated with each floating gate transistor in a memory cell has been removed from the cell and combined with other select transistors to provide a single select transistor for use with a plurality of floating gate transistors. As disclosed in the '657 application, the select transistor is typically an N-channel transistor, while the EPROMs comprise floating gate transistors. Accordingly, the process for manufacturing the array requires two separate masking sequences, one to fabricate the floating gate EPROM transistors and another to fabricate the N-channel select transistors. The N-channel select transistors must be more robust and capable of pulling down a larger current than the EPROM transistors.
Fabricating two different types of transistors during the manufacture of a semiconductor EPROM memory array complicates the manufacturing process and reduces yield. Accordingly, a way is required to reduce the process complexity and thereby increase the yield of the array.